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| NTE8542 Integrated Circuit Tri-State Quad I/O Register General Description: The NTE8542 is a 4-bit storage register with two terminals per bit which may be used as either inputs or outputs when tied to two bus lines. Storage capability is obtained with positive edge triggered flip- flops having common clock and asynchronous clear. Each I/O terminal can be forced to a high impedance state (Hi-z state) using the Output Disable controls. Features: D Series 54/74 compatible D Input clamp diodes D Propagation delays . . . . . . . 25ns D Power dissipation . . . . . . 400mW D Operation . . . . . . . . . . . . . 40MHz Absolute Maximum Ratings: (Note 1) Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0V Input Voltage, Vi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V Output Voltage, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C Lead Temperature (Soldering, 10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300C Recommended Operating Conditions: Parameter Supply Voltage Temperature Symbol VCC TA Min 4.75 0 Max 5.25 +70 Unit V C Note 1. "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device operation. Electrical Characteristics: (Notes 2 and 3) Parameter Logical "1" Input Voltage Logical "1" Input Current Logical "0" Input Voltage Logical "0" Input Current Input Clamp Voltage Logical "1" Output Voltage Output Short Circuit Current Logical "0" Output Voltage Supply Current TRI-STATE I/O Current with Inputs and Outputs Disabled Propagation Delay to a Logical "0" from Clock to Output Propagation Delay to a Logical "0" from Clear to Output Propagation Delay to a Logical "1" from Clock to Output Delay from Disable to High Impedance State (from Logical "1" Level) Delay from Disable to High Impedance State (from Logical "0" Level) Delay from Disable to Logical "1" Level (from High Impedance State) Delay from Disable to Logical "0" Level (from High Impedance State) Maximum Clock Frequency Enable to Clock Set-Up Time Enable to Clock Set-Up Time tpd0 tpd0 tpd1 t1H Symbol VIH IIH VIL IIL VCD VOH IOS VOL ICC Test Conditions VCC = Min VCC = Max, VIN = 2.4V VCC = Max, VIN = 5.5V VCC = Min VCC = Max, VIN = 0.4V VCC = Min, IIN = -12mA VCC = Min, IOUT = -800 VCC = Max, VOUT = 0V, Note 4 VCC = Min, IOUT = 16mA VCC = Max VCC = Max, VIN = 2.4V VCC = Max, VIN = 0.4V RL = 400, CL = 50pF TA = 25C RL = 400, CL = 50pF TA = 25C RL = 400, CL = 50pF TA = 25C RL = 400, CL = 5.0pF TA = 25C RL = 400, CL = 5.0pF TA = 25C RL = 400, CL = 50pF TA = 25C RL = 400, CL = 50pF TA = 25C RL = 400, CL = 50pF TA = 25C RL = 400, CL = 50pF TA = 25C RL = 400, CL = 50pF TA = 25C Min 2.0 - - - - - 2.4 -25 - - - - - - - - Typ Max Unit - - - - - - - - - - - 23 24 25 6.0 - 40 1.0 0.8 -1.5 - -70 0.4 120 40 -40 35 36 38 15 V A V V V mA V mA A ns ns ns ns -1.0 -1.6 mA t0H - 15 25 ns tH1 - 20 30 ns tH0 - 17 25 ns fMAX tSO tSI 30 20 20 40 13 12 - - - MHz ns ns Electrical Characteristics (Cont'd): (Notes 2 and 3) Parameter Date to Clock Set-Up Time Date to Clock Set-Up Time Data to Clock Hold Time Data to Clock Hold Time Minimum Clock Pulse Width Minimum Clear Pulse Width Symbol tSO tSI tHO tHI PWMIN PWMIN Test Conditions RL = 400, CL = 50pF TA = 25C RL = 400, CL = 50pF TA = 25C RL = 400, CL = 50pF TA = 25 RL = 400, CL = 50pF TA = 25C RL = 400, CL = 50pF TA = 25C RL = 400, CL = 50pF TA = 25C Min 10 5.0 10 5.0 20 20 Typ Max Unit 4.5 -4.0 4.5 -3.5 - - - - - - - - ns ns ns ns ns ns Note 2. Unless otherwise specified min/max limits apply across the 0C to +70C range for the NTE8542. All typicals are given for VCC = 5.0V and TA = 25C. Note 3. All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to GND unless otherwise noted. All values shown as max or min on absolute value basis. MODE OF OPERATION: CLEAR 0 0 0 0 0 0 0 DIS1 0 1 0 1 X X X DIS2 1 0 0 1 X X X E1 1 1 1 1 0 1 0 E2 1 1 1 1 1 0 0 A1 - 4 Q Hi-z Q Hi-z Data QN Data B1 - 4 Hi-z Q Q Hi-z QN Data Data Comments Output Data to Bus A Output Data to Bus B Output Data to Both Buses Store Data With Outputs in Hi-z State Enter Data From Bus A Enter Data From Bus B Enter Data From Both Buses (Logic "1" on Either Will Dominate) Clear 1 X X X X X X X = Don't Care State QN = Data After Clock Transition Pin Connection Diagram DIS2 A1 B1 B2 A2 E2 E1 GND 1 2 3 4 5 6 7 8 16 VCC 15 DIS1 14 A4 13 B4 12 B3 11 A3 10 Clock 9 Clear 16 9 1 8 .870 (22.0) Max .260 (6.6) Max .200 (5.08) Max .100 (2.54) .700 (17.78) .099 (2.5) Min |
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